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NSC History A long time goal of artificial intelligence (AI) is the development of methods that can learn from examples to recognize events and make decisions. For example, automatic recognition of speech is already in widespread use, although this technology is far from usable in ordinary conversations. Another example is the recognition of handwriting; here the technology is still primitive. The eventual wide-spread consumer use of decision making machines and robotics will depend on the development of powerful, inexpensive, trainable devices which will allow the evolution towards thinking machines with capabilities far in excess of today's speech processors and robots. NSC was founded to exploit a trainable high-speed technology called NSC Detectors that is inexpensive to implement for recognition and decision making. NSC Detectors could form a basis for widespread use of broader AI technology. Consider a digital device that performs recognition and outputs a yes or a no when the input is a digital word. For example, the input might be numbers that are parameters characterizing an electrocardiogram (ECG) beat, and the device must decide if the beat is a dangerous arrhythmia. When a sequence of bits is input to a logic circuit, which then outputs a 1 or a 0, (e.g., answers yes or no), the circuit is called a switching function. All digitally implemented pattern recognizers (such as neural networks) that have a binary output are, in fact, switching functions. The word "trainable" means that examples of known categories (e.g., both dangerous and normal ECG beats) and a training algorithm can be used to organize the device. The trained device will give the correct answer (classification) when presented with examples where the category is not known. A key to NSC's technology is the development of efficient training algorithms that can organize binary logic into complex switching functions by using only binary inputs from known categories. The number of categories need not be restricted to two; NSC has constructed logic for up to sixteen categories. During NSC Detectors training many binary numbers (millions in the case of hard disk drives or digital communications) are input to the training algorithm, along with their correct classifications. The algorithm determines the exact logic structure that gives the correct classifications with the minimum number of gates. The NSC Detectors implementation can be done in a number of ways: 1. Combinations of AND and OR gates. This is suitable for ECG arrhythmia detection in implantable defibrillators because very little power is required. It is also suitable for hard disk drives and digital communication channels where minimizing the number of gates is important. 2. Field programmable gate arrays (FPGA). This implementation has been for radar type classification using pulse shapes. The logic can be reconfigured in microseconds to follow additional training. 3. Single chip ASICs. These can be developed to have the same reconfiguration characteristics as FPGA-based NSC Detectors. 4. Serial computer such as a DSP. These can be programmed with the NSC Detectors. Training algorithms have been developed to classify multiple categories where the number of gates in multi-category logic is only slightly larger than the number required for two categories. All four of the above methods can be used to implement multi-category logic, NSC Detectors.

A flurry of conventional neural network hardware development occurred during the 1990s that used analog, digital and hybrid technology. NSC is aware of 17 different efforts, none of which is now commercially available. All of these developments implemented neuron analogs that required multiplication, addition, weight storage and non-linearities. The resulting complexity is a cause of the high casualty rate. Another cause is the sometimes failure of conventional training algorithms to converge to useful solutions when the pattern sets are complex. It is intriguing to think of creating processors by organizing a set of neuron analogs that perform a cognitive function. Consequently, most workers in the field approach the problem by applying a biological model. However, just as bird wings are not suitable for airplanes, neuron analogs may be far less suitable than NSC Detectors for many pattern recognition applications. B. Application Examples Several applications of NSC detectors are listed below. 1. Ventricular Arrhythmia Warning Sets of ECG parameters recorded from pacemakers and defibrillators implanted in a small number of patients were provided by a major Corporation. NSC Detectors was trained to recognize ECG waveforms that occurred prior to an arrhythmia. The success rate was 90%. A much larger number of examples will be required to show the real viability. 2. Printed Character Recognition Back Propagation Neural Networks (BPNN) and NSC Detectors were compared in recognizing printed characters. The training of the NSC Detectors was significantly easier than the BPNN training, and the NSC Detectors have the best performance with noisy characters. 3. Automatic Recognition of Communication Signal Modulation Type Both BPNN and NSC Detectors were trained to give an alert when a specific shortwave radio modulation type occurred. Both performed nearly equally well, but real-time implementation of the NSC Detectors would be significantly less complex. 4. Aircraft Versus Land Vehicle Sound Recognition Both NSC Detectors and BPNN were trained to discriminate between aircraft and land vehicle sounds. Performance of the two was the same; however, significantly fewer gates would be required to construct the NSC Detectors. 5. Sonar Sound Classification NSC Detectors were trained to recognize various sonar sounds. The performance was as good as that of human operators, and the NSC Detectors never become fatigued. 6. Radar Type Classification NSC Detectors were trained to classify radar types by recognizing frequency modulation and pulse shapes of radar pulses. FPGA hardware was constructed that could classify 100,000 pulses per second. An equivalent ASIC could classify over 1,000,000 pulses per second. This project demonstrated that powerful high-speed NSC Detectors could be constructed on a single chip. In these examples where there was a comparison with a BPNN, the number of BPNN weights exceeded the number of NSC Detectors binary logic elements by factors of up to 20. And, of course, the operation of a binary logic element is far faster than a weight multiplication. NSC Officers & Board Members >>

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